Welcome to today’s podcast, where we discuss a critical topic for the industry: closing reliability gaps in complex analog and mixed-signal IC designs. We’ll explore Siemens’ Insight Analyzer, a tool that enables early analysis to catch issues before they escalate. Joining us is Matthew Hogan from Siemens, who will share insights on how Insight Analyzer enhances design processes and supports engineers in achieving greater reliability. If you work in analog reliability or power-aware design, this conversation is a must-listen. Let’s get started!
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ES: You are listening to EE Times On Air, and this is EE Times Current. I’m Eric Singer. Today’s episode is brought to you by Siemens EDA.
Today we are talking about something that is top-of-mind for a lot of you: closing the reliability gaps in increasingly complex analog and mixed-signal IC designs—and doing it earlier, faster, and more systematically.
As designs become more heterogeneous and integration of IP blocks more intricate, traditional simulation and ERC tools often aren’t enough. They’re reactive by nature, catching issues too late in the flow—when rework them is costly, and design intent is harder to trace.
That’s part of why “shift-left” verification has become more than just a buzzword. We talk about it a lot on this show, and it’s because it’s a strategic necessity. And today’s conversation is all about one of the tools helping to make that shift actionable: Siemens’ Insight Analyzer.
Insight Analyzer operates pre-layout, performing topological state-based analysis directly on the netlist. It automatically identifies structures like logic gates, current mirrors, level shifters, and latches—without simulation—to uncover leakage paths, floating nodes, and domain crossing issues before you get to sign-off. It’s not just fast—it’s early, and that’s the point.
Joining me to go deep on this is Matthew Hogan. Matthew is Product Management Director for Calibre Design Solutions at Siemens Digital Industries Software, with over two decades of design, field and product development experience. He actively works with customers who have an interest in Calibre? PERC?, Insight Analyzer, IC reliability verification and other reliability topics. Matthew also actively volunteers his time with IEEE and other organizations. He has been the past general chair for both the International Electrostatic Discharge Workshop and the International Integrated Reliability Workshop. He has previously been on the Board of Directors for the ESD Association, contributes to multiple working groups for the ESDA, and is an industry advisor to the Center for Advanced Electronics Through Machine Learning. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a bachelors in engineering from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University.
In our conversation, Matthew walks through how Insight Analyzer complements existing Calibre PERC flows—bringing reliability analysis closer to the designer, not just the sign-off team. We talk about how the tool integrates into analog design environments like Cadence and Siemens Custom IC, how its automatic circuit recognition provides visibility into circuit intent, and how teams are using it to catch subtle parasitic leakage and domain-crossing issues that often go undetected by simulation alone.
He is also shares a case study from a team that found ten critical issues right before tapeout—just by running a basic power check in Insight Analyzer. That alone speaks volumes about what’s possible when verification starts earlier in the flow.
If you’re responsible for analog reliability, domain crossings, or power-aware design intent and you’re looking for ways to reduce rework and accelerate sign-off, this conversation is really going to be worth your time.
Let’s get into it.
MH: Thanks, Eric. Glad to be here.
ES: So let’s start by discussing a little bit about how Insight Analyzer differs from traditional tools in this space.
MH: Well, Insight Analyzer is used very early in the design process. Some of your more traditional tools like Calibre PERC are used when you’ve got a complete circuit, or maybe even while you’re in the layout aspect of your design. By having a look at the design early with your pre-layout netlist, Insight Analyzer’s able to perform topological state-based checking that looks at the circuit as a whole. Many traditional solutions look at individual devices and how they’re connected. We’ve got of course SPICE simulation, which simulates the functionality and structures of your circuit systems. But it doesn’t necessarily give you a good indication as to whether or not you might be susceptible to different types of errors or challenges. So Insight Analyzer automatically recognizes and understands structures like logic gates and latches and current [wearers] and level shifters in the design to help you understand the big picture, and how well it’s going to work, particularly from a leakage perspective. So it’s a very innovative and compelling technology that we’ve had a lot of designers use, not only in their design process, so that they can make sure that they’re getting the design as correct as possible, but then also used for final sign-off and verification as well, to make sure that when they put all of their circuit elements together, they’re getting the best product that they can.
ES: So it sounds like this holistic view fits nicely with something we certainly talk a lot on this program about, which is shift-left. You’re able to catch things early in the design process, particularly leakage. I was impressed by some of the case studies on that aspect of things. Who is using Insight Analyzer? It’s intended for designers?
MH: Yeah, absolutely. And you’re right. It fits very nicely in with the shift-left initiative that we’ve got, particularly on the Calibre side, driving consistency faster for your overall verification cycle times. The technology really allows you to have a look, as you say, on the leakage side of things, and really understand, is there a structural challenge or problem with the circuit elements that I have in place so I need to do something different because of the process notes that I’m on, and how do I make sure that I’m providing the best possible circuit structures for my circuit as I’m going through and validating the design there? But it’s definitely the designers that are looking at this, looking to improve the quality of their circuit, with this very compelling verification technology that we have with Insight Analyzer, and making sure that their circuit has been constructed correctly. And before they go off and even test the functionality of it, in what can often be very long running SPICE simulations. The SPICE technology has gotten considerably better over the last decade, and we can run lots of very fast SPICE analyses. But you also need to be very sensitive to the input vectors that you’re using for SPICE. And because of the holistic way that Insight Analyzer has looked at these circuits, it’s able to identify and bring to a designer attentions lots of subtle design areas like leakage that might otherwise be overlooked.
ES: Yeah. Let’s look a little more closely at how a circuit designer would use this. Is this something that they’re launching from within their Cadence environment?
MH:??? Yeah, it is. So you do your analog design from a transistor level inside of Cadence or even Custom IC from Siemens, and once you’ve got your transistor configurations all set up, before you go and do your simulation, what we recommend is customers run Insight Analyzer, have a look at the structures and the elements that are there, and make sure that they haven’t missed anything obvious and in, like we said, say with leakage, any of these subtle issues that might come into play as well. So we can go through and help provide guidance and advice on if there are any floating gates or nets or nodes, any high impedance issues that they need to be looking at. Are they missing level shifters? Are they across these different power domains, all well before they start getting into this simulation environment? So it’s analog designers, in their analog design environment, launching this and being more productive, and really making best use out of that simulation time that they’re looking for when they have a look at the functionality of their circuit.
ES: How difficult or not difficult is it to get up and running with the Insight Analyzer tool?
MH: It’s pretty easy for an analog designer to get into the Insight technology. As you mentioned, from their cadence environment, or if they’re using the Siemens Custom IC design tools as well, they can launch into the Insight Analyzer environment with their netlist. They set up isolation cells. They very quickly define different power domains and voltage levels. And then they utilize the core technology of Insight Analyzer, which is to go through and do the analysis and circuit identification, and present you back with results based on the different types of analyses that you want to do. Analog and digital designs are treated very similarly, and the user just selects what type of analyses they want to do, and they get some very easy to interpret results coming back. We have a great schematic visualizer which identifies for them the exact location of where these challenges are happening in the design, and based off that, they’re able to go through and figure out, do we need to change the circuit, make something more robust, or is this an acceptable risk that they want to live with based on the circuit performance criteria that they have?
ES: So we’ve touched briefly on looking at level shifters and logic gates. Take us a little more into what features that Insight Analyzer has that set it apart.
MH: Absolutely. So it has some built-in automatic circuit recognition. Before running any checks, Insight Analyzer will automatically recognize the functional pieces in the netlist the way a human would. This includes level shifters and logic gates, analog structures, and the tool then uses this automatic recognition during checking to understand the circuit. It’s a useful sanity check, so the user can see exactly how the tool is understanding their design. So if you’ve recognized some level shifters, and you notice that, hey, hang on, there’s one of the shifters I thought that were in the design aren’t being recognized, you can go and chase those down and then understand, well, why aren’t they being recognized as level shifters? Maybe they’re misconfigured. Maybe they don’t have complete definitions in there. And the designer can then go through and really have a much better understanding of their design and what challenges they might have. There’s also results visualization, where we can draw that schematic of the results, give the user an instant picture of what the problem might be. And the schematic shows everything that they need to see for the cause of a problem, but really nothing extra. We’ve tried really hard to pare it down to just the essentials, so there are no distractions there for these analog designers looking to validate their systems and really help them with the process of creating quality designs.
ES: That idea of the schematic being pared down to really only what’s relevant seems incredibly compelling to me.
MH: And it becomes even more important when you’re integrating different blocks from different design owners. Because you might not be the owner of a block that you’re integrating with that is now flagging a result. So you don’t know necessarily the hidden details of what’s in there, and just really showing you exactly, this is where the issue is, allows you to either debug and fix that yourself, or go to the other design team or the designer themselves, say hey, this is what I found when we’re integrating these different parts together. And it really allows you a greater dialogue, and to be data-driven when you have these collaborations with others.
ES: I love that idea of breaking down those silos and taking this holistic view of the entire ecosystem. Do you have any success stories from folks who are using this already that you can share to give us some more specific context?
MH: Absolutely. Just last week, a user told us that they found ten real circuit problems during their tapeout, which to me is astonishing, because there’s a lot of verification that goes through this whole entire design process. So, just from running our most basic check called power connections, which finds voltages and connectivity issues. That’s not even including some of the more complex state-based analyses like conditional floats and other things that we look at. The user was able to find a serious leakage problem in a Bluetooth SoC, which, when you have a look at all these portable devices, these always on devices, really managing leakage, particularly in the radios and the communication systems that we have, they’re very complicated systems in themselves. To reduce the leakage, to be able to bring that power profile down, is paramount. So they were checking for parasitic leakage. They were running full chip at the SOC level. They found these parasitic leakage issues when the main supply was turned off, but the backup power supply was turned you. Right? So sneaky little backup power that you weren’t really anticipating. And the leakage, a current traveled through that on backup supply through several stages, including the power switch, and then through a body diode of a pass gate which was biased incorrectly into the off position of the main supply, which is expecting at zero volts. So most of these damaging problems that the users are finding often occur due to an obscure combination of factors that were missed in simulation or you didn’t really think would be possible, but we’re able to find those and highlight them for these designers to go through and then be engineers, and be presented with this information, again be data driven, and make good choices about their circuit, and understand how do we mitigate these types of issues holistically from the entire SOC perspective.
ES: Matthew, a lot of our listeners are already using the Calibre PERC suite. Can you touch a little bit on how this complements that suite of reliability verification tools?
MH: Absolutely. Well, our Siemens Calibre PERC software has been a market leader for decades, mostly focused on the manufacture and reliability sign-off. We’re focused very much on ESD in those flows, getting foundry rule decks, and making sure that you can do IC sign-off. We’re expanding those solutions into the designer space, consistent with that Calibre shift-left initiative, driving designers faster into the overall verification cycle for our customers. And the Insight Analyzer technology has been a pioneer in that space, addressing designer-specific circuit reliability and bringing a new and more efficient analysis model to the industry. The combination of the Insight technology and Calibre PERC really creates this wonderful continuum from early design verification with the schematic in the designer space, particularly if you’re an analog designer, identifying some very subtle type issues that might otherwise go missed, all the way through final physical verification where you’ve got those polygons and ESD structures in place, and you’re leveraging Calibre PERC foundry design off decks. So, each of these technologies really complement each other to form an entire continuum throughout the verification journey that you have in your circuits, all the way from the block level to final SOC sign-off.
ES: That’s a really powerful argument again for that holistic view and seeing the entire design process from that high level, and again catching thing earlier. So Matthew, I really want to thank you for walking us through this today and giving us some pretty compelling case studies there. We really appreciate you joining us today.
MH: Thanks so much, Eric. It’s been delightful being here, and thanks again so much for giving us the opportunity to showcase this compelling technology of Insight Analyzer.
ES: And listeners, if you want to learn more, we’ve got links in the show notes for how you can find out more all about it. Thanks again, Matthew.
MH: Thanks so much, Eric.
ES: That brings another episode of EE Times Current to its end. Thank you for listening, and thanks again to our guest, Matthew Hogan. EE Times Current is available through the major podcast platforms, but if you get to us at our website at eetimes.com, you’ll find a transcript along with direct links to the other stories we’ve mentioned and other resources. EE Times Current is produced by EE Times. It was engineered by Taylor Marvin at Coop Studios. I’m Eric Singer. Thanks for listening.
